1. Field of the Invention
The invention relates to a semiconductor structure and a manufacturing method thereof, and particularly relates to a package structure and a manufacturing method thereof.
2. Description of Related Art
The electronic devices nowadays heavily rely on circuit boards where semiconductor dies or integrated circuits (ICs) are disposed. Mechanical and electrical connections between dies and substrates constantly bring challenges to IC designers. Wire bonding is one of the techniques that are commonly used to connect the ICs and substrates.
FIG. 1 is a schematic view illustrating a conventional package structure. The structure includes a substrate 10, a multi-die stack structure 12, a plurality of first pads 14a to 14h, vertical wires 16a to 16h, and a second pad 18. The multi-die stack structure 12 includes, from bottom to top, dies 12a to 12h vertically stacked on the substrate 10. The die 12a is a bottom die, whereas the die 12h is a top die. The first pads 14a to 14h are respectively disposed on an active surface of the corresponding dies 12a to 12h. The vertical wires 16a to 16h are respectively disposed on the corresponding first pads 14a to 14h. The second pad 18 is disposed on a surface of the substrate 10 at a side of the multi-die stack structure 12.
In a process of forming the vertical wires 16a to 16h, a distance from the top die 12h to the second pad 18 is longer than a distance from the bottom die 12a to the second pad 18. Accordingly, a length of the vertical wire 16h is also greater than a length of the vertical wire 16a. The higher the vertical wire 16h disposed on the top die 12h, the more likely a wire sweep may be resulted in. To prevent the higher vertical wire 16h from being pressed and damaged by a sealant mold chase afterwards, a depth of a cavity needs to be increased, making a polishing cost increase as well.